Designing a BCD adder & subtractor with HDL

In computer based electronic items binary number system is used. But the human readable format is decimal number system. Binary coded decimal is a digital encoding mechanism to convert binary data between machine and human readable formats. To convert decimal data to binary, binary coded decimal adder subtractors are used in those electronic items. In this post I show you how to design a BCD adder subtractor using HDL (Hardware Descriptive Language) and here I use ‘Verilog’ language. Gate level design is the approach used to develop the BCD adder.

Here is the flow diagram of the circuit.

Because the gate level design is used in this example the whole implementation is done using logic gates.

1-bit full adder

Here I start from the basic unit which is 1 -bit full adder. As shown in figure it has 3 inputs (A, B, Ci) and 2 outputs (S, Co). This circuit has designed using 2 XORs, 2 ANDs and 1 OR gate.

//define a 1bit fulladder
module fulladd(a, b, c_in,sum, c_out);
  input a, b, c_in;
  output sum, c_out;
  wire s1, c1, c2;
  xor (s1,a, b);
  and ( c1,a, b);
  xor (sum,s1, c_in);
  and (c2,s1, c_in);
  or (c_out,c2, c1);
endmodule

4-bit full adder

In the next step I combine 4 1 -bit full adders to create the 4-bit full adder as shown in figure. In this configuration it has 4bits per each input with a carry in has 4bit output with a carry out.

//define a 4-bit full adder
module fulladd4(a, b, c_in,sum, c_out);
  //i/o port declaration
  input [3:0] a, b;
  input c_in;
  output [3:0] sum;

  output c_out;
  //internal net
  wire c1, c2, c3;
  fulladd fa0(a[0], b[0], c_in, sum[0], c1);
  fulladd fa1(a[1], b[1], c1, sum[1], c2);
  fulladd fa2(a[2], b[2], c2, sum[2], c3);
  fulladd fa3(a[3], b[3], c3, sum[3], c_out);
endmodule

1-digit BCD adder

Here arithmetic operations are done using BCD number format. Hence the result of normal binary addition should convert to BCD format using error correction methods as shown in figure. For this configuration I use two 4-bit binary adders, 2 AND gates and 1 OR gate. In the error correction, 0110 binary 6 should add to the result of normal binary addition to convert the result in BCD format.

module bcd_adder( A, B, CIN, F, COUT);
  input [3:0] A, B;
  input CIN;
  output [3:0] F;
  output COUT;
  wire [3:0] Z,S;
  wire k,w1,w2,w3;
  fulladd4 add0(A, B, CIN, Z, k);
  and (w1,Z[3],Z[2]);
  and (w2,Z[3],Z[1]);
  or (COUT,k,w1,w2);
  assign S = {1'b0,COUT,COUT,1'b0};
  fulladd4 add1(Z, S, 0,F,w3);
endmodule

9’s compliment generator

Since the final circuit is made for both addition and subtraction operations, I'm going to make a special circuit with mode selection. 2’s compliment method is used for binary subtraction. But in BCD it must be 9’s compliment method. As shown in figure I have designed 9’s compliment generator in the following manner. 

9 - B = X 

Here is the logic used in 9’s complement generator.

X3 = B3M’ + B3’B2’B1’M
X2 = B2M’ + (B2’B1 + B2B1’) M
X1 = B1
X0 = B0M’ + B0’M

module complement_generator(B, M, x);
  input [3:0]B;
  input M;
  output [3:0]x;
  wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
  xor (x[0],B[0],M);
  assign x[1]=B[1];
  xor (w5,B[1],B[2]);
  and(w9,w5,M);
  not (w1,M);
  and (w6,B[2],w1);
  or (x[2],w9,w6);
  not (w2,B[1]);
  not (w3,B[2]);
  not (w4,B[3]);
  and (w8,M,w2,w3,w4);
  and (w7,B[3],w1);
  or (x[3],w8,w7);
endmodule

1-digit BCD adder subtractor

Combining the above 9’s compliment generator and the BCD adder it is able to design the 1 -digit BCD adder subtractor as follows.
 

module add_sub(A, B, CIN, M, F, COUT);
  input [3:0]A,B;
  input CIN,M;
  output [3:0]F;
  output COUT;
  wire [3:0]W;
  complement_generator comgen0(B,M,W);
  bcd_adder add0(A, W, CIN, F, COUT);
endmodule